1. Field of the Invention
The invention relates generally to output circuits and interface systems comprising the same and, more particularly, to output circuits driving a load in response to an applied signal and interface systems comprising the same.
2. Description of the Background Art
FIG. 7 is a diagram showing a conventional output circuit included in a semiconductor integrated circuit device (referred to as CMOSIC hereinafter) comprising a CMOS circuit. The output circuit 100 is a CMOS inverter type output circuit (a driver).
The output circuit 100 comprises N channel MOS transistors 101 and 102, inverters 103, 104, and 105 and an output pad 106. Driving capability of the inverters 103, 104, and 105 respectively, is increased according to the order. A capacitive load 107 outside the IC is connected to an output pad 106. As shown in FIG. 8, each of the inverters 103, 104, and 105 comprise a P channel MOS transistor 108 and an N channel MOS transistor 109.
Generally, the capacitive load is assumed to be the load of these CMOS inverter type output circuits (referred to as the CMOS output circuit hereinafter) for the following reasons.
(1) Usually, the CMOSIC is connected as a load in the CMOS output circuit. In the input circuit of the CMOSIC, the current such as a base current in a TTL (Transistor-Transistor Logic) circuit does not flow. Therefore, an input impedance of the CMOSIC is equivalent to the capacity.
(2) The input circuit of the CMOSIC connected to the CMOS output circuit is assumed to receive a voltage of 5 V amplitude. Thus, generally in the CMOS output circuit, a low level V.sub.OL of the output signal is determined to be 0 V, and a high level V.sub.OH of the output signal is determined to be 5 V. As shown in FIG. 9, it is assumed that the load connected to the output pad 106 comprises a resistive load 111. In this case, when the transistor 108 in the output circuit 100 (see FIG. 8) turns on, a potential V.sub.L of a node nL is represented by the next equation: EQU V.sub.L =R.sub.L .multidot.V.sub.DD /(R.sub.ON +R.sub.L)
where, R.sub.ON is on resistance value, V.sub.DD is resistance value of the power supply potential, and R.sub.L is resistance value of the resistive load 111.
In this manner, the output voltage of the output circuit 100 changes dependent on resistance value R.sub.ON of the transistor included in the output circuit 100 and on resistance value R.sub.L of the resistive load 111.
Transistors have various on resistance values due to various conditions during manufacturing. Therefore, when resistive load is connected to the CMOS output circuit, the output voltage may have various values. In addition, the output voltage having the amplitude of 5 V can not be obtained.
For the reasons mentioned above, the resistive load is not connected to a conventional CMOS output circuit, and the interface between the CMOSICs does not comprise the resistive load.
As mentioned above, there is no resistive load connected to the conventional CMOS output circuit. Thus, the interface between the CMOSICs is in a high impedance state, and therefore it is easily influenced by noises from other signals.
In addition, as shown in FIG. 10, let us assume that the output circuit 100 and the input circuit 120 are connected through a transmission path 130. If the impedance of the transmission path is 50.OMEGA., and the terminal resistance of resistance value 50.OMEGA. is connected to the end of the transmission path 130, impedance match can be obtained between the transmission path 130 and the input circuit 120. However, for the reasons mentioned above, since the resistive load is not connected to the CMOS output circuit, impedance match is not obtained between the transmission path 130 and the input circuit 120. Therefore, reflection of the signal is likely to occur, and high speed transmission of 50 MHz or higher is difficult to attain.